Intellectual property (IP) core based design is an emerging design methodology to deal with increasing chip design complexity.\r\nC/C++ based high level synthesis (HLS) is also gaining traction as a design methodology to deal with increasing design complexity.\r\nIn the work presented here, we present a design methodology that combines these two individual methodologies and is therefore\r\nmore powerful. We discuss our proposed methodology in the context of supporting efficient hardware synthesis of a class of\r\nmathematical functions without altering original C/C++ source code. Additionally, we also discuss and propose methods to\r\nintegrate legacy IP cores in existing HLS flows. Relying on concepts from the domains of program recognition and optimized\r\nlow level implementations of such arithmetic functions, the described design methodology is a step towards intelligent synthesis\r\nwhere application characteristics arematched with specific architectural resources and relevant IP cores in a transparent manner for\r\nimproved area-delay results. The combined methodology is more aware of the target hardware architecture than the conventional\r\nHLS flow. Implementation results of certain compute kernels froma commercial tool Vivado-HLS as well as proposed flow are also\r\ncompared to show that proposed flow gives better results.
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